Regviz

Raspberry Pi /RP2350 /TIMER0 /DBGPAUSE

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Interpret as DBGPAUSE

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (DBG0)DBG0 0 (DBG1)DBG1

Description

Set bits high to enable pause when the corresponding debug ports are active

Fields

DBG0

Pause when processor 0 is in debug mode
DBG1

Pause when processor 1 is in debug mode

Links

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Register License

Copyright © 2024 Raspberry Pi Ltd.

SPDX-License-Identifier: BSD-3-Clause

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data